Memories are critical to conventional Application-Specific Integrated Circuits (ASIC). As integrated circuit technology advance, the complexity and density of circuit devices formed within a single integrated circuit (IC) has increased dramatically. Consequently, several problems have arisen with regard to testing ICs. For example, while the conventional testing methodologies for a memory array within an IC may be relatively straight forward, ICs typically have far fewer I/O pins available to an external circuit tester than are required to adequately test the memory array.
A general solution to the above-described and other difficulties with external testing is to embed test circuitry within the IC itself. Such integrated testing facilities are frequently referred to as built-in self-test (BIST), array self-test (AST), or array built-in self-test (ABIST) circuits and will hereinafter be referred to generally as BIST circuits.
Although the integration of BIST circuits within ICs facilitates IC testing, a central concern associated with BIST circuits is the large amount of die size consumed by the BIST circuit and associated circuitry. This concern is magnified as the number of memory arrays and other sub circuits integrated within an IC that requires BIST testing multiply. This concern is particularly significant for state-of-the-art integrated circuits, such as a microprocessors and Application-Specific Integrated Circuits (ASICs), which commonly contain hundreds or thousands of relatively small memory arrays each requiring BIST testing.
One conventional system uses a common controller which controls the test activities on the entire chip while supporting a broad range of memory types like single port, dual port, register files and ROM. This is possible only due to a proper partitioning of the whole BIST system. However, the shared approach of this integrated circuit has a lot of parallel connections and hence occupies a lot of area due to routing congestion.
The concept of BIST is used for at-speeds equivalent to its application speed. Having a controller per BIST to run the desired algorithm as well as manage the repair activities will result in increased area and hence an increase in overall testing cost. Also more efforts will be needed at the time of chip integration. Thus various state of the art solutions are being given to share the test and repair resources across the plethora of memories on the chip. But then due to improper partitioning of the whole structure, the ultimate implementation becomes cumbersome as well as routing congestion prone as well as less than at-speed.
In existing architectures, the controller is embedded inside the BIST which controls the test activities. As the algorithm for testing single and dual port memories are different, the controller inside the BIST is hard coded for the desired algorithm. Thus, the controller's architecture changes from one memory type to other. As these controllers are replicated, for all the memories it results in lot of silicon area.
FIG. 1 depicts a conventional shared BIST architecture 100. In architecture 100, a common controller 101 interacts with only the tester. The different memory groups each have their own different controllers or have dedicated collars for the algorithm. In the latter case, all the memories are connected in parallel which increases the routing congestion and thus makes the BIST architecture highly floor plan dependent.
Accordingly, conventional systems and methods occupy a lot of area and experience routing congestion due to the various parallel connections between the memories. Conventional approaches make the BIST highly floorplan dependent and thus limit sharing memories which are physically close to each other. In addition, memories of different clock domain cannot be shared. For smaller conventional memories with large word widths, the gains are relatively small because the collar area cannot be reduced. Accordingly, gains cannot be shared between various memories nor can different types of memories be shared.
At-speed testing is not easily possible using conventional systems and methods. Either significant areas are wasted to achieve the at-speed testing or at-speed testing is simply not possible. Moreover, integration is a big issue for the user as the BIST area and performance becomes chip floor plan dependant. As more parallel lines are running for long distances, BIST defects can itself lower the yield of the chip. Conventionally shared BIST methodology is not easily programmable or even if programmability was possible, a lot of area is wasted.
The conventional BIST architectures are either dedicated BISTs or shared BISTs. In a dedicated BIST, a controller, which controls the test activities, is embedded inside the BIST. The algorithm for testing single or dual port memories is hard coded into the controller. Thus the controller's architecture changes from one memory type to another. As these controllers are replicated, for all the memories, it results in lot of silicon area. This lead to the development of shared BISTs.
In a shared BIST, there is a common controller that interacts with the memories to be tested. Different memory groups either have different controllers or dedicated collars for the algorithm. All the memories are connected in parallel and this result in increased routing congestion and the BIST architecture is highly floor dependent. Also synchronous transmission of data between a central controller and wrappers placed near a memory introduce power loss.
Sometimes sharing is not possible because of the physical orientation and layout. Thus it becomes a challenging task to share the BIST among different memories placed in different parts of a chip.
Further, different memories on the chip may execute on different clock domains and sometimes on totally uncorrelated clocks. This leads to a situation wherein either the BIST cannot be shared or at-speed test is not possible and thus loosing the fault coverage. Hence, the BIST architecture should be partitioned in such a manner, that the at-speed components are not shared.
With the shrinking technology, newer defects like Vt-mismatch, resistive bridging, etc., has developed which results in multiple read failure, data retention failure, etc. Test clock routing is another challenge that needs to be taken into consideration, as it has to be balanced and clock tree routing is required.
Conventional architectures based on serial architecture have been proposed to achieve floor plan independence. But, they do not allow asynchronous transfer and are not programmable. Moreover, the conventional architectures that are programmable are not sharable.
There is a need for a common controller to control the test activities on the entire chip while supporting a broad range of memory types like single port, dual port, register files and ROM.